It really doesn't matter. The biggest benefit of ARM are the fixed length instructions and only Apple is actually taking advantage of this by decoding 8 instructions at once. The big question is whether decoding that many instructions is actually a benefit. It's entirely possible that branch prediction and other factors are greater bottlenecks that have to be tackled first to take advantage of the faster instruction decoding.
Intel's Pentium processors (the original ones) were doing pretty badly because they made the pipeline too deep at the expense of other things.
I think the original Pentium had the pretty much canonical 5 stage pipeline. It did pretty well. Its successor, the Pentium Pro, an OoO design, was deeper but also did amazingly well.
You are probably thinking of the Pentium 4 which was designed as a speed demon with a very deep pipeline and failed to reach its target frequency.
Anandtech's article indicates they have an out-of-order buffer of around 630 entries (Zen 3 is only 256 entries). The M1 has 7 integer math ports and 4 FP/SIMD math ports plus several bunch of load/store/branch ports . It seems like they could completely saturate those decoders given the right code.
Fair points, but I think we can be 100% certain that Apple has modelled this and made their architectural decisions based on this modelling - especially as they are no the 10th or so iteration of their designs.
That and that their CPUs are designed to run one OS and apps are developed against one set of libraries. This frees them to tune the hardware to the needs of the software much more than any other manufacturer can do (a PC needs to run Word and Autocad equally well)
They have certainly optimised against some key aspects of their software (eg Rosetta and reference counting) but that is not at the expense of other software. The M1 Arm CPUs are just very fast general purpose CPUs.
Intel's Pentium processors (the original ones) were doing pretty badly because they made the pipeline too deep at the expense of other things.